The MicroCore Labs MCL51 was tested in three stages:

During the first stage, an exhaustive set of tests was written in assembly code which would exercise each 8051 opcode and then observe the results. PSW flags were checked whether or not the instruction generated a change in their status and all four register banks were cleared and rechecked to guarantee that the opcode did not affect registers or memory outside of the intended destination. Each boolean instruction was run on multiple memory ranges that support bit-mapped operations while mathematic and string  instruction were run against all possible data values.

After these tests were developed they were run against multiple simulation tools, some of them major vendors. I was interested to find that some of the tools were not 100% correct for every 8051 instruction!  Who the vendors are and what are the errors? I’m not telling. 🙂

Once the tests were validated against multiple vendor simulators I then wired up a system to run the tests on real silicon. I chose a ROM-less 8051 variant that came in a 40-pin package and had 3.3V IOs.  This allowed be to connect it directly to an FPGA test board which you see below:

 

The test code uses simple loops when it reaches a failure, so it was easy to run the test and simply look at the scope to see if it was running in any infinite loops. When it looped to a final address it showed that all of the tests had run successfully. The test code is nearly 6KB so it was divided into three sections and tested independantly.

After the test code was validated by known correct simulators and real silicon I was then ready to run it against the MCL51 core in my Verilog simulation environment. I am pleased that while a few subtle bugs were corrected in the MCL51 core using this test suite, I am now very confident that the core is 100% compatible and correctly implements the 8051 instruction set!

Please visit us at: www.MicroCoreLabs.com for more information.

The MicroCore Labs MCL51 is now available!

The MCL51 is an ultra-small footprint, microsequencer-based, 8051 instruction-set compatible, embedded processor core that can be implemented in any FPGA or ASIC technology.

Key Features:

• 100% Compatible with 8051 instruction set
• Vectored interrupts with up to 128 sources
• Proxy addressing for peripherals to allow any bus size
• Bus Interface Unit allows high degree of peripheral customization

The MCL51 is an embedded processor core implemented with a high performance 32-bit microsequencer which utilizes less than 200 Xilinx LUTS and a single block RAM. It is 100% compatible with the classic 8051 instruction set and has a Bus Interface Unit (BIU) that provides the maximum degree of flexibility to implemented SFR registers and peripherals customized to the user’s design. Improvements to the original 8051 include up to 128 vectored interrupts as well as a proxy addressing system which allows the user to connect peripherals of any bus width to the core.

The core was run against a rigorous suite of tests which were validated using a major simulation tool as well as on genuine 8051 hardware.

The demonstration video of the MCL86 core running on the Lattice XO2 Breakout Board has been posted to YouTube. The FPGA is the XO2-7000 which is around $10 USD.

Here it is:   MCL86 8086 core running on Lattice XO2 Breakout Board

 

 

The video demonstrates how the MCL86 core, 2KB of RAM and a UART are all that is needed to create a practical embedded control processor with a host interface.

The total register utilization is a modest 8% of the $10 Lattice XO2-7000 which leaves most of the FPGA’s registers available for important user logic.

The MCL86 is about as small as you can get when it comes to embedded processor cores that support a practical instruction set.

Please visit us at: www.MicroCoreLabs.com

Here are some tools that have been verified to work on Linux and/or Windows 7. Some of them are DOS tools which can run under DOSBox.

Assembly:  A86 (DOSBox),  MASM (DOSBox),  NASM (Linux/Windows 7),  as86 (Linux), emu8086 (Windows 7)

C/C++:   Open Watcom (Windows 7),  bcc (Linux)

My preference is to write in assembly code and use A86 to generate a .COM file which I can simply copy into the FPGA code ROM.

 

 

Due to popular demand we have run the MCL86 through Xilinx ISE targeting the Spartan-6 series FPGAs.

The MCL86 coupled with a fully-loaded 8088 BIU easily fits in an XC6SLX16 consuming 4% of the slices at a speed of over 100Mhz.

For designers using the MCL86 with minimal BIUs the footprint would be even smaller…

 

We just coupled the MCL86 core with an optimized Bus Interface Unit (BIU) and ported it to the Lattice XO2 Breakout Board where it consumes 551 (8%) of the XO2-7000’s registers.

This system-on-a-chip consists of the MCL86 EU core, on-chip RAM/ROM, and a UART and leaves 92% of this $10 FPGA’s registers unused and available

A YouTube video of it running will be posted soon!

Well over 100,000 page views to date of Steve Liebson’s blog posting on the MCL86 core. Cool!!!

8088 microprocessor IP core fits in 308 LUTs, runs at 180MHz on a Kintex-7 FPGA

The MCL86 is a 16-bit, microsequencer based, cycle and structurally compatible, soft IP core of the 8086/8088 microprocessor.  Like the original processor, the MCL86 Execution Unit (EU) is separate from the Bus Interface Unit (BIU) which allows it to be utilized in a wide range of applications from a drop-in 8086/8086 replacement to a highly customized system-on-a-chip. The MCL86 consumes a minimal amount of space and power which leaves the majority of the silicon available for user logic. 

The MCL86 EU core utilizes only 308 LUTs which is less than one percent of the smallest Kintex FPGA and less than ten percent of the Lattice XO2-7000 FPGA. Block RAMS are used to hold the microcode.

The MCL86 core has been extensively tested on desktop computer hardware which demonstrates the robustness of the core. Please see our Links page for YouTube videos of the MCL86 running desktop applications on real hardware. We have also developed an exhaustive test suite to ensure the core accurately emulates the original processor.

The core has the option to be cycle compatible with the original 4.77Mhz 8088 microprocessor which allows the MCL86 to be a drop-in replacement. If this is not enabled then the core can execute instructions significantly faster.

The core’s extremely small footprint makes it ideal for embedded applications where a microcontroller is required that draws the minimum of power and logic resources. It runs the legendary x86 instruction set which has the support of thousands of books, tools, and other resources. Millions of desktop computers and embedded applications have been developed around this processor which make it a ideal choice for an embedded FPGA or ASIC controller.

The project source-code is on GitHub: https://github.com/MicroCoreLabs/Projects/tree/master/MCL86